AT86RF231
11.8
11.8.1
11.8.2
Dynamic Frame Buffer Protection
Overview
The AT86RF231 continues the reception of incoming frames as long as it is in any receive state.
When a frame was successfully received and stored into the Frame Buffer, the following frame
will overwrite the Frame Buffer content again.
To relax the timing requirements for a Frame Buffer read access the Dynamic Frame Buffer Pro-
tection prevents that a new valid frame passes to the Frame Buffer until a Frame Buffer read
access has ended (indicated by /SEL = H, refer to Section 6.2 “SPI Protocol” on page 19 ).
A received frame is automatically protected against overwriting:
? in Basic Operating Mode, if its FCS is valid
? in Extended Operating Mode, if an IRQ_3 (TRX_END) is generated
The Dynamic Frame Buffer Protection is enabled, if register bit RX_SAFE_MODE (register
0x0C, TRX_CTRL_2) is set and the transceiver state is RX_ON or RX_AACK_ON.
Note that Dynamic Frame Buffer Protection only prevents write accesses from the air interface -
not from the SPI interface. A Frame Buffer or SRAM write access may still modify the Frame
Buffer content.
Register Description
Register 0x0C (TRX_CTRL_2):
The TRX_CTRL_2 register is a multi purpose register to control various settings of the radio
transceiver.
Bit
7
6
5
4
3
2
1
0
+0x0C
RX_SAFE_MODE
Reserved
OQPSK_DATA_RATE
TRX_CTRL_2
Read/Write
Reset Value
R/W
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
? Bit 7 - RX_SAFE_MODE
If this bit is set Dynamic Frame Buffer Protection is enabled:
Table 11-17. Dynamic Frame Buffer Protection Mode
Register Bit
RX_SAFE_MODE (1)
Value
0
1
Description
Disable Dynamic Frame Buffer Protection
Enable Dynamic Frame Buffer Protection
Note:
1. Dynamic Frame Buffer Protection is released with the rising edge of pin23 (/SEL) of a Frame
Buffer read access, see Section 6.2.2 “Frame Buffer Access Mode” on page 20 , or radio trans-
ceiver state changing from RX_ON or RX_AACK_ON to another state.
This operation mode is independent of the setting of register bits RX_PDT_LEVEL, refer to Sec-
tion 9.1.3 “Configuration” on page 102 .
? Bit [6:2] - Reserved
? Bit [1:0] - OQPSK_DATA_RATE
Refer to Section 11.3 “High Data Rate Modes” on page 137 .
154
8111C–MCU Wireless–09/09
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